1. Field of the Invention
This invention relates to semiconductor devices and, in particular, to dielectrically isolated semiconductor devices.
2. Art Background
In most electronic components, such as integrated circuits, electrical isolation is produced between regions of essentially single crystal silicon by junction isolation. (Single crystal silicon is silicon having defects, e.g., linear and planar defects such as dislocations or stacking faults, respectively, in a density through the crystal of less than 10.sup.8 defects per cm.sup.2.) In this junction approach, lateral isolation is accomplished by interposing between the active single crystal silicon regions, a region of opposite electrical type from that of the active region. The thickness of this added region is approximately equal to the depth of the active regions of the single crystal materials being separated. Similarly, vertical isolation in the junction isolation approach is obtained by the presence of material of opposite conductivity type positioned below the active region. (The active region is that portion of the single crystal silicon which is ultimately modified to contain electronic device structures. The active region is typically 1 .mu.m thick for nominal voltage devices, e.g., devices operating at less than 30 V.) Such rectifying junctions formed at the boundaries of the active regions provide lateral and vertical isolation when appropriately biased.
For some applications lateral junction isolation is replaced with lateral dielectric isolation to save space and to reduce capacitance. (Lateral dielectric isolation entails the presence of an insulator rather than a material of opposite conductivity type at the lateral boundaries of the active region.) By expedients such as junction isolation or lateral dielectric isolation, transistors or other devices formed in one single crystal region, i.e., one active region, are electrically isolated and are prevented from interacting with devices in a second active region.
However, for some significant applications the use of junction isolation, or a combination of junction and lateral dielectric isolation, is not sufficient. For example, in some instances, the voltage employed in operation is often large enough to cause electrical breakdown between separate active regions. This electrical breakdown occurs through many paths such as by the penetration of charge carriers below one active region through the underlying substrate, across the substrate under the lateral isolation region, and into the second active region. When a typical junction isolation structure is employed, the voltages encountered in some applications, such as telephone line interface circuits, are sufficient to cause breakdown by charge carrier penetration through the isolating regions. To prevent such undesirable electrical interaction between two active regions, a combination of lateral and vertical dielectric isolation is employed. This dielectric isolation is provided by surrounding the single crystal silicon regions with an electrically insulating dielectric material. By this expedient, interaction between active regions even at high voltages is avoided. Additional advantages are also available by replacing junction isolation completely with dielectric isolation. Typical junction isolation introduces significant capacitance into the structure. It is possible in theory to increase the insulating capability of junction isolation to prevent breakdown in high-voltage devices. However, a high-voltage application requires a correspondingly high resistivity in the junction isolation region. Since the size of the depletion region increases with both voltage and resistivity, enhanced breakdown characteristics require an extremely large volume devoted to isolation. This large volume imposes a penalty both in the required volume per device and in increased parasitic capacitance. The substitution of dielectric isolation for junction isolation greatly reduces the area requirement, thereby reducing cost, and also reduces capacitance, allowing faster device operation.
A variety of processes have been employed to produce semiconductor components having dielectric isolation. These processes are designed not only to produce dielectric and lateral isolation but also to produce a relatively planar surface upon which further processing is performed to form devices in the active regions. (If the surface is not planar, subsequent device processing is considerably complicated.) Most of these processes involve the formation of a relatively thin dielectrically isolated active region. Generally, the thicker the active region the more difficult it has been to dielectrically isolate. One predominant method has been employed for thick active regions. (Thick active regions for the purpose of this disclosure are considered those with a thickness greater than 3 .mu.m.) This dielectric isolation process to produce relatively thick active regions is described by K. E. Bean and W. R. Runyan, Journal of the Electrochemical Society, 124, 5C (1977). However, because of the strictures imposed by the requirements of dielectric isolation and planarity, this process involves a large number of complicated steps and introduces a high density (10.sup.4 cm.sup.-2 to 10.sup.5 cm.sup.-2 ) of crystal defects and impurities. Additionally, the conditions employed in this technique often lead to significant bowing of the wafer being processed, e.g., bowing greater than 75 .mu.m across a 3 inch-wafer and 200 .mu.m across a 4 inch-wafer. This bowing, in turn, causes wafer breakage during subsequent processing. Thus, the manufacturing yields are low and costs are high for defect and impurity-sensitive devices fabricated by this process.